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ATDH2225 FPGA
Table 1. 10-pin Header Pin Location on Target Board
1(DATA)
3(SCLK)
5(SW1)
7(GND)
9(NC)
2(CE)
4(RESET/OE)
6(SW2)
8(VCC)
10(SER_EN/GND)
Notes:
1. Pin 10 activates "SER_EN" on target board.
2. Pin 9 is the polarizing pin (cut off).
3. The 10-pin header is 0.1' spacing
Pin 5 and Pin 6 of the 10-pin header are the two signals which able to decode for cas-
cading up to 8 devices. The latest CPS software has the ability to control the 2 signals
SW1, SW2 and by using the A2 pin of the device, you can select up to 8 devices. There-
fore, you could use a 2-to-4 decoder to cascade 8 devices using our existing ISP circuit
(see Figure 3).
Figure 3. ISP of Cascaded AT17C/LV002s in AT40K FPGA Applications
Vcc
Vcc
Vcc
Vcc
Vcc
Vcc
DATA
1
2
CE
SCLK
3
4 Reset/OE Vcc
SW1
5
6
SW2
0
1
2
3
SW1
2-to-4
decoder
SW2
#5 AT17C/LV002
Vcc
7
9
GND
#1 AT17C/LV002
8
10
DATA
RESET/OE
DATA
RESET/OE
CEO(A2)
CE
CLK
CEO(A2)
CE
CLK
SER_EN
READY
SER_EN
READY
VCC
FPGA
#7 AT17C/LV002
#3 AT17C/LV002
RESET
RESET
DIN
DATA
DATA
CEO(A2)
INIT
RESET/OE
RESET/OE
CON
CE
CEO(A2)
CE
CLK
CCLK
CLK
SER_EN
READY
CLK
SER_EN
READY
M2
M1
M0
VCC
GND
#6 AT17C/LV002
#2 AT17C/LV002
DATA
RESET/OE
DATA
RESET/OE
CEO(A2)
CE
CLK
CEO(A2)
CE
CLK
SER_EN
READY
SER_EN
READY
VCC
#8 AT17C/LV002
#4 AT17C/LV002
DATA
RESET/OE
DATA
RESET/OE
CEO(A2)
CE
CEO(A2)
CE
CLK
CLK
SER_EN
READY
CLK
SER_EN
READY
3
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